| 1. | A dynamic reconfigurable system based on cpci bus
总线的动态可重构系统 |
| 2. | Micro - task processing in heterogeneous reconfigurable systems
异构可配置系统中的微任务处理 |
| 3. | In the future i will address issues in reconfigurable systems ; programming models ; security , trust and privacy ; and reflective middleware
当前主流的中间件是基于面向对象的客户服务器泛型。 |
| 4. | Morphosys : an integrated reconfigurable system for data - parallel and computation - intensive applications . ieee trans . computers , may 2000 , 49 : 465 - 481
当前的要求促进了csoc的使用，它可以通过集成可配置可重用和可编程硬部件的方法实现。 |
| 5. | In the vector mode , all part of the design is implemented in the reconfigurable system ; stimulus and response vector is transferred serially to and from hardware . this mode improves the verification
测试向量模式是将整个被验证设计全部都下载到硬件平台上,测试向量以数据流的形式在软件环境和硬件平台之间传递,对被验证设计施加测试向量和接收响应。 |
| 6. | Use fft as an example algorithm , analyze the structure of the algorithm to build the reconfigurable system and to implement the design . the pipeline thinking was used in the schema . 3 . puts forward two schemes related to float multiplier , and compares them
本论文参考了现有的几种典型乘法器结构，提出两种乘法器结构方案，并进行比较分析，在满足性能指标的同时，还考虑了体积、功耗、等因素，在此基础上，进行了可重构技术应用的研究。 |
| 7. | Co - emulation speed is also tested . in the co - emulation mode , a part of the design is simulated in the hardware simulator , the rest part of design are emulated in the reconfigurable system , two part of the design work cooperated to accelerate the verification speed
联合验证模式将soc设计按照模块进行划分,将其中的一部分设计下载到硬件平台中,而其余设计驻留在硬件仿真器中,两部分协同工作,利用硬件较计算机仿真器的速度的优势,提高对被验证系统的验证速度。 |
| 8. | < 4 > validates the designs of des / rsa on the reconfigurable system test board , and discusses the further optimized approach of the designs . the research results will be contributive to the reconfigurable computing research in the field of encryption application of our nat ion
本课题的设计与实现以航空微电子中心的可重构计算系统为硬件环境，此系统由通用处理器和现场可编程阵列逻辑组成，是混合系统，在当前一些应用领域如嵌入式微处理器系统等具有非常看好的应用前景。 |
| 9. | The key to the fft algorithm is the design of butterfly computation and that of the address logic . the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ) , basing on these , we do our research on reconfigurable technology . the result indicates that the data processing ability of reconfigurable system improved greatly
结果表明，可重构系统在数据处理能力方面比以往的系统有了很大的提高，本设计实现的fft重构处理器可工作于60mhz下，完成一个16点fft需要132个主时钟周期，完成32点fft需要324个主时钟周期，而且具有一定可重构性，可以方便地将其运算点数进行扩展，或将其他的图像处理算法在实时处理系统中实现。 |
